1. Field of the Invention
The present invention relates to a memory control system having the interface of a volatile semiconductor memory.
2. Description of the Related Art
Memory control systems of this type include a control device of a large capacity hard disk drive and a data control device of a network. Such memory control systems, while transmitting no data, enter sleep to reduce their power consumption. During sleep, clock signals are suspended, and the system-controlling processors (such as a CPU) and control circuits connected to the processors stop operating.
In general, a processor has a sleep command, and fetches the sleep command to stop the reception of the clock signal to put itself into sleep. When the processor contains a PLL (Phase-Locked Loop), the fetch of the sleep command makes the PLL stop the operation of generating a system clock signal. The suspension of the system clock signal stops the operations of the control circuits in the processor and other control cores in the chip which receive the system clock signal, as well as other chips connected to the chip, thereby putting the system into sleep.
By the way, in situations where a memory control system is connected with volatile semiconductor memories such as a DRAM, there has been the problem that the contents retained in the memories can be destroyed if the processor simply fetches a sleep command to stop the generation of the system clock signal. In particular, if the memory control system is connected with clock synchronous SDRAMs (synchronous DRAMs), even a brief stop of the system clock signal causes the SDRAMs to malfunction, destroying the retained data.
In order to avoid the foregoing defect, when a memory control system connected with volatile memories such as an SDRAM is to be put into sleep, the volatile memories must be put into a data retaining mode such as a self refresh mode before the suspension of the system clock signal. Specifically, system programs to be executed by the processor need to include a processing program for putting the SDRAMs into the self refresh mode in advance of the sleep command, so that the volatile memories are previously put into the self refresh mode before the processor fetches the sleep command.
Here, even in the cases where the system programs are stored in the SDRAMs, at least the sleep command and the processing program for entering the self refresh mode must be stored in another memory. The reason for this is that if the processing program and the sleep command were stored in the SDRAMs, the execution of the processing program would put the SDRAMs into the self refresh mode, precluding the read of the sleep command. That is, the processor would not enter sleep.
Accordingly, in situations where the system programs are stored in the SDRAMs, there has been the problem that the system programs must be stored into both the SDRAMs and other memories, with complicated software processing. In particular, the program developers are heavily burdened since they need to develop the software upon a beforehand comprehension of these procedures and timing.